This invention relates to integrated circuits and, more particularly, to integrated circuits where control of variability in the effective size of elements within the integrated circuits enhances the operation of such circuits.
Substantial variations can occur in the performance of integrated circuits simply because the manufacturing processes that are employed can not be carried out with the desired precision. Indeed, it is not uncommon to find substantial performance variation between integrated circuits of identical design that are manufactured on a single semiconductor wafer but at a different location on the wafer. This includes variations in delay, speed (frequency response) and power consumption.
Designers who intend to use integrated circuits must account for all possible variations in ICs' performance. Consequently, in many circumstances designers develop worst case designs, which are designs that assume all IC parameters, or characteristics, to be at their worst specified levels. Manufacturers specify the minimum and maximum values in both speed and power characteristics of their ICs. That means, of course, that the manufacturer must assure itself somehow that the integrated circuits do lie within the promised bounds of operational characteristics. In turn, that means that integrated circuits which lie outside the promised bounds have to be discarded as "defective".
Clearly, being able to narrow the variation in speed and power consumption of manufactured ICs would result in higher yield for the IC manufacturer and more desirable integrated circuits for the designer.
Whereas in bipolar ECL technology circuit means can be provided for self-control of the power dissipation within the integrated circuits, no such circuit means are available for MOS integrated circuits because of their inherently different mode of operation. The only solution for MOS circuits is, as indicated above, to select the integrated circuits that match the specifications, after those circuits have been manufactured.
An issue that is related to speed and power dissipation of elements throughout the integrated circuit is the issue of creating specific impedances that are presented at input/output terminals of the integrated circuits. This issue encompasses both digital and analog signals (i.e., both digital and analog ICs) and encompasses terminals that transmit signals as well as terminals that receive signals.
When signals exit an IC terminal, flow along a signal path over an appreciable distance and enter another IC terminal, signal reflections can be experienced from impedance discontinuities along at any point along the signal path, and specifically from the terminals. Most reflections can cause considerable problems in both digital and analog environments (e.g., mis-detection of digital signals). It is well known, however, that when the signal path is viewed as a transmission line with a characteristic impedance, undesirable reflections are eliminated when the transmission line is terminated at the sending and/or receiving ends with impedances having a value equal to the characteristic impedance of the transmission line. In other words, what is needed for effective transmission of very high frequency signals through signal paths of appreciable length is integrated circuits where both input and/or output terminals have specified and well controlled impedances.
The most general requirement for such termination impedances is that the impedance be the same for both positive and negative signals. A somewhat weakened version of this requirement is permitted when the circuit either delivers or expects to receive signals of a single polarity. One example of this situation is found when the integrated circuit delivers power in digital form (either delivers some power, or delivers no power). The same applies when the circuit absorbs power. Only when power is delivered must the output impedance be equal to the transmission line characteristic impedance. Also, even in the absence of a transmission line, it is well known that for optimum power transfer the output impedance of a signal source must equal the load impedance.
In an article titled "A Self-Terminating Low-Voltage Swing CMOS Output Driver", IEEE Journal of Solid-State Circuits, Vol. 23, No. 2, pp. 457-464, April 1988, Knight et al. described one CMOS circuit arrangement for developing a digital signal at an output terminal that is characterized by a specified and controlled output impedance. The output buffer of their arrangement consists of a series connection of a P-channel transistor having its drain connected to the drain of an N-channel transistor, while the sources of the two transistors are connected to their respective power supplies. The junction point where the drains of the two transistors are connected is also connected to the output terminal. The gate of each of the transistors is driven by a separate pre-drive circuit, and the pre-drive circuits enable and control their respective transistors in an alternating fashion. More specifically, each pre-drive circuit sets the gate-to-source voltage of its respective transistor to a specified level to insure that the transistor presents a predetermined impedance to the terminal.
Each of the pre-drive circuits is a digital inverter connected between a fixed voltage source and a variable voltage source. Each pre-drive circuit is also responsive to a digital input signal. The digital signal of one pre-drive circuit is the logical inverse of the digital signal of the other pre-drive circuit.
The Knight et al. arrangement suffers from a number of deficiencies because each of the pre-drive circuits requires a controllable analog voltage, and since the levels for this voltage must be maintained under changing operating conditions, the circuitry for creating this voltage is difficult to design, comprises a substantial number of components and consumes a considerable amount of power. Noise is also a problem.